1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory capable of rapid and stable operation by stepping up a current.
2. Description of Prior Art
An ordinary type of a ROM (read-only memory), (hereinafter called the "ordinary type ROM") has an equivalent circuit as shown in FIG. 5. This ROM has memory cells M consisting of MOSFETs located in a matrix, connected to word lines WL1, WL2, . . . and WLM extending along the rows through gates of each memory cell M, and connected to bit lines B1, B2, B3, . . . , Bi and Bi+1 extending along the columns through sources s and drains d. A source and a drain of adjacent memory cells are connected to a bit line consisting of a diffused layer so as to reduce the chip area.
For example, to read the memory cell M shown by the arrow in FIG. 5, the bit line B2 is connected to a sense amplifier (not shown) with the word line WL1 kept at a high level and the bit line B1 at a ground level. Thus, data 1 or 0 is read when the memory cell M is turned on or off, respectively.
A disadvantage of this ordinary type ROM is that the diffused resistor of a bit line depends greatly upon the position of the memory cell M in the memory cell array, therefore, a discharge current in reading is unstable, which slows the reading speed. All the junction capacitances of the memory cells aligned along the columns are equal to the parasitic capacitance of the bit lines, which also slows the reading speed, thereby increasing of the number of memory cells connected to bit lines.
Recently a ROM having a parasitic capacitance decreased by dividing the memory cell arrays into plural banks as shown in FIG. 6 (hereinafter called the "bank type ROM") has been proposed. In this ROM, banks Bm 2i-1, Bm+1 2i-1, . . . and Bm 2i, Bm+1 2i, . . . shown in broken lines in FIG. 6 are constructed by dividing every column of the memory cell arrays along the columns. Sub-bit lines SBm 2i-2, SBm 2i-1, SBm 2i, . . . consisting of diffused layers are disposed between the adjacent banks, and each of sub-bit lines is connected to the memory cell M in each bank in the same manner as the bit lines of the ordinary type ROM shown in FIG. 5. These sub-bit lines are also connected to the main-bit lines MBi-1, MBi,. . . extending along the columns via bank selector transistor MOSFETs (transfer gate transistors) QOm 2i-2, QOm 2i-1, QOm 2i, . . . The main bit line consists of a metal layer with low-resistance, and two sub-bit lines are connected together to one main-bit line.
For example, to select the first memory cell M which belongs to the odd-numbered bank Bm 2i-1, the main-bit line MBi-1 is grounded and the main-bit line MBi is connected to a sense amplifier. The bank selection signal indicating the selection of the bank Bm 2i-1 is kept on a high level, with the bank selection MOSFETs QOm 2i-2 and QOm 2i-1 on, and the sub-bit lines SBm 2i-2 and SBm 2i-1 is connected to the main-bit lines MBi-1 and MBi, respectively. Then data in the memory cell M is read with the word line WL1 on a high level. In this way, the bit lines are constructed with the main-bit lines and sub-bit lines, and the route of a diffused layer (the sub-bit line) is divided along the columns so as to decrease wiring-resistance of a bit line. Therefore, a discharge current is stepped up enough to effect a high speed read operation. The bit lines can have a reduced parasitic capacitance, and as a result, the memory capacity is increased because of the increased junction capacitance of the memory cell M in every column divided in the direction of columns.
However, in a conventional bank type ROM, as shown in FIG. 4, the memory is read through three MOSFETs, that is, the memory cell M and two bank selection MOSFETs QOm 2i-2 and QOm 2i-1. Therefore, the on-resistance of the transistor is more increased than in the ordinary type ROM having a single memory cell M on the discharge route, thereby increasing the whole resistance although the diffused resistance (resistance r.sub.1) of a bit line is small. Thus the discharge current becomes small for reading. Accordingly, the read operation slows down.